# Prefix the include dirs with '-I' when passing them to the compilerĬFLAGS += $( addprefix -I, $(INCLUDE_DIRS) ) # Set some compiler flags we need. include $(DEP_FILES) # List of include dirs. d extensionĭEPFLAGS = -MMD -MP -MF Include the dependency tracking files # named the same as the target file with the. ![]() d dependency-tracking files when we compile. d, $(OBJ_FILES) ) # Flags to generate the. d extension addedĭEP_FILES = $( addsuffix. OBJ_FILES = $( addprefix $(BUILD_FOLDER)/, $(SRC_FILES.c=.o) ) # Generate a list of depfiles, used to track includes. Larger projects might use a wildcard to locate # each line, makes it easy to add files later (and makes it easier to see Putting this in a separate variable, with a file on PHONY : all : $(BUILD_FOLDER)/example # List of C source files. # Default all rule will build the 'example' target, which here is an executable Ifeq ($(V),1) Q := else Q := # The build folder, for all generated output. # Makefile for building the 'example' binary from C sources Otherwise track for example, when unpacking a toolchain: You may see the touch command used to track rules that seem difficult to Out-of-tree behavior by outputting the generated files in a build directory %.o : %.c # create the directory tree for the output file □ echo mkdir -p $( dir ) # compile $(CC) -c $^ -o recommend avoiding use of VPATH. # like `src/test.c` when running from the build directory! # $(OBJ_FILES) will be built by the pattern rule belowįoo.a : $(OBJ_FILES) $(AR) rcs $(OBJ_FILES) # pattern rule since we added ROOT_DIR to VPATH, Make can find prerequisites OBJ_FILES = $( subst $(MAKEFILE_DIR)/, $(SRC_FILES.c=.o) ) # now we can continue as if Make was running from the root directory, and not a VPATH += $(MAKEFILE_DIR) SRC_FILES = $( wildcard $(MAKEFILE_DIR)/src/ *.c ) # Set the obj file paths to be relative to the cwd MAKEFILE_DIR = $( shell dirname $( realpath $( firstword $(MAKEFILE_LIST) ))) # now inform Make we should look for prerequisites from the root directory as # Derive the directory containing this Makefile # This makefile should be invoked from the temporary build directory, eg: There’s so much behavior happening behind the scenes. PHONY targets are ALWAYS considered out-of-date, so Make willĪLWAYS run the recipe for those targets (and therfore any target that has a # prerequisite! Make will make sure (pardon the pun) the build rule executes PHONY : build build : foo foo.a # a phony rule that runs our test harness. # a phony rule that builds our project just contains a prerequisite of the using the # variable here to specify the rule target 'foo.a' $(AR) rcs foo-lib.o # use ar to create a static library containing our object file. # compile foo-lib.c into a library 'foo.a'įoo.a : foo-lib.c # compile the object file $(CC) foo-lib.c -c foo-lib.o PHONY : all all : build test # compile foo.c into a program 'foo' You can specify a particular makefile with the -f/-file argument: Make will search for files named GNUmakefile, makefile, and Makefile, in that Running make will load a file named Makefile from the current directoryĪnd attempt to update the default goal (more on goals later). Meson, or another modern build system a more pleasurable experience. In these situations, you might find using
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